1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which is formed in silicon layer located on an insulating layer, or on a silicon-on insulator (SOI) substrate.
The present application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2001-160597, filed May 29, 2001, which is herein incorporated by reference in its entirely for all purposes.
2. Description of the Related Art
A field effect transistors are now typically formed on the SOI substrate (which is called an SOI-FET) instead of the more conventional bulk semiconductor substrate. The SOI-FET is formed in the thin silicon layer (the SOI layer) which is formed on the insulating layer of the SOI substrate. Since a junction capacitance is reduced by such a structure, the SOI-FET can operate at a high-speed. Particularly, a fully depleted SOI-FET formed in the SOI layer is known as a low-power device which has a small parasitic capacitance and a sub-threshold swing which is smaller than that of the conventional bulk semiconductor substrate. The fully depleted transistor has a depletion layer that expand to the bottom surfaces of a source region and a drain region, when a voltage is supplied to a gate electrode thereof. Since an expansion of the depleted layer of the fully depleted SOI-FET is defined by a thickness of the. SOI layer, a short channel effect can be inhibited. Thus, the thickness of the SOI layer is reduced to achieve the fully depleted operation of the SOI-FET.
Such a fully depleted SOI-FET having the source and drain regions in the SOI layer is constructed with an island shaped full isolation structure by performing an element isolation process, for example a local oxidation of silicon process (a LOCOS process). A region between the source and drain regions is called a body region. The body region is basically depleted when the fully depleted SOI-FET is operating.
Since a thickness of a channel depleted layer is determined in accordance with the thickness of the SOI layer, it is necessary reduce the thickness of the thinner SOI layer. When an extremely thin SOI layer (e.g. 10 nm) is formed, defects may arise due to a heat treatment process which is performed at a temperature of 900° C. or more. The heat treatment may cause a void to be opened in the SOI layer due to a thermal aggregation (also called a thermal agglomeration), and an upper surface of the insulating layer under the SOI layer might be exposed. Such a void generated by the thermal aggregation is disclosed in the magazine article of the lecture presentation of the 47th Applied Physics Association, pp. 884, 30p-YK-9, “Initial Stage of Thermal Agglomeration of an Ultrathin SOI”, published in March, 2000. If a subsequent dry etching process forming a contact hole were performed on an SOI substrate having such a void, the void might extend through the insulating layer and be formed in the conductive substrate under the insulating layer. If such a void were formed at the edge of the SOI-FET, the drive current of the SOI-FET might be reduced, since a parasitic resistance of the source and drain regions would be increased so as to increase a resistance between the source and drain regions.
Further more, if a contact plug consisting of a metal material is formed in the contact hole, and a wiring layer connecting the contact plug is formed over the SOI substrate, since the contact plug is also formed in the void, the source and drain regions and the silicon substrate might be electrically shorted.
FIGS. 6(a) through 6(c) and 7(a) through 7(c) are cross-sectional views showing a conventional method of manufacturing a semiconductor device. An SOI substrate 101 includes a silicon substrate 101a, an embedded oxide layer 101b and a thin silicon layer 101c (an SOI layer 101c). As shown in FIG. 6(a), field oxide regions 102 and highly doped impurity regions 108a and 108b are formed in the SOI layer 101c, and gate electrodes 105a and 105b and side walls 107a and 107b are formed over the SOI substrate 101. The highly doped impurity layers 108a and 108b are formed by an implantation of impurity ions.
Then, a heat treatment is performed to activate the ion-implanted impurities at a high temperature. At this time, as shown in FIG. 6(b), the highly doped impurity layers 108a and 108b gradually aggregates since the temperature of the heat treatment is equal to or more than an aggregation temperature of the SOI layer 101c consisting of silicon. As such, when the SOI layer is ultra-thin, upper surfaces R of the embedded oxide layer 101b become partly exposed.
Next, as shown in FIG. 6(c), refractory metal silicide layers 109a and 109b are formed by a conventional silicide process.
Next, as shown in FIG. 7(a), an interlayer insulating layer 110 is formed over the SOI substrate 101.
Next, as shown in FIG. 7(b), contact holes 111a and 111b are formed by an anisotropic etching, for example, a dry etching such as a reactive ion etching (RIE). At this time, since the embedded oxide layer 101b is partly exposed, a void 113 is formed extending through the embedded oxide layer 101b and reaching an upper surface of the silicon substrate 101a. As a result, since a parasitic resistance of the highly doped impurity layers 108a and 108b increases so as to increase a resistance between the highly doped impurity layers 108a and 108b, and the drive current of the SOI-FET is reduced.
Next, as shown in FIG. 7(c), a contact plug 112a consisting of a metal material is formed in the contact holes 111a and 111b, and a wiring layer 112b connecting the contact plug 112a is formed over the SOI substrate 101. At this time, since the contact plug 112a is also formed in the void 113, the highly doped impurity layer 108a and the silicon substrate 101a are electrically shorted.
The conventional SOI-MOSFET is disclosed in an article of Proceeding 1995 IEEE International SOI Conference, Oct. 1995, pp.116-117, “Characteristics of Submicrometer LOCOS Isolation”, published on October, 1995.